Method and apparatus for the management of queue pointers by multiple processors in a digital communications network

ABSTRACT

A method for managing a buffer queue that stores a data queue, wherein the data queue comprises a set of n data elements, n being at least zero. A head pointer is stored at a first location, which may be in a cache controlled by a first processor. The head pointer indicates a head buffer of the buffer queue. The first processor reads the head pointer to determine the head buffer of the buffer queue when a data element is to be removed from the data queue. The first processor reads a next pointer of the head buffer to determine whether the data queue is empty. The first processor determines that the data queue is empty when the next pointer has a first value, which indicates that the head buffer is a dummy buffer.

FIELD OF THE INVENTION

[0001] The present invention relates generally to data storagemanagement and more particularly to the management by multipleprocessors of queue pointers that indicate the beginning and end of aqueue.

BACKGROUND OF THE INVENTION

[0002] Cell switching is a method of transmitting information wherein arelatively large unit of information called a “frame” is broken intosmaller, equal sized units of information called “cells.” A frame istypically segmented into cells by the Segmentation And Reassembly (SAR)unit of a source node from which the frame originates. The source nodeserially transmits each cell of a frame to a destination node through adigital communication network constructed of communication lines,switches, and intermediate nodes that forward the cells to thedestination node. An SAR unit of the destination node reassembles theframe using the transmitted cells after all cells of a frame have beenreceived.

[0003] Digital communication networks have a limited amount of bandwidthsuch that only a certain amount of information can be transmitted acrossthe network per unit time. One consequence of limited bandwidth iscontention for network resources, and one solution for such contentionis to store cells until network resources become free, at which time thestored cells may be transmitted to their destinations. To ensure thatframes are correctly reconstructed by the destination node, stored cellsmust be queued such that they are transmitted in the order that theywere segmented (or received).

[0004] According to one mechanism for storing cells, one or more memorydevices are provided as a “buffer pool” comprising a multiplicity of“buffers.” Each buffer is of a fixed size, and each buffer stores asingle cell. A buffer may also store associated control informationrequired for queuing and routing the stored cell. Wherein each buffer isassociated with a memory location, ordering is not implied by the memoryaddress of a buffer. Instead, buffers are queued by creating andmaintaining linked lists of buffers.

[0005] The control information for each buffer includes a “next pointer”that allows the creation of a linked list of buffers as cells arestored. For example, when a first cell is stored in a first buffer tobegin the queue, the next pointer of the first buffer is set to a nullvalue, indicating that the first buffer is the last buffer of the queue.When a second, sequentially received (or segmented) cell is stored in asecond buffer, the next pointer of the first buffer is modified toindicate or “point” to the memory location of the second buffer, and thenext pointer of the second buffer is set to a null value to indicatethat the second buffer is the end of the queue. Next pointers may bestored by the buffers or in a separate next pointer array.

[0006] Wherein the next pointers of the buffers provide the generalorder of the queue, a “head pointer” specifies the “head” or beginningof the queue, and a “tail pointer” specifies the “tail” or the end ofthe queue. When a new buffer is added to a queue, the tail pointer ofthe queue is set to indicate the new buffer as the tail of the queue.Similarly, when a buffer is removed from the queue, the head pointer isset to the buffer pointed to by the next pointer of the removed buffer.

[0007] Because buffers are often simultaneously added to and removedfrom the queue, a first processor is typically responsible for addingbuffers to the queue, and a second processor is typically responsiblefor removing buffers from the queue. The first processor may be calledthe “queuing processor,” and the second processor may be called the“servicing processor.”

[0008] According to a traditional approach of the prior art, whenever abuffer is to be removed from a queue, the servicing processor firstdetermines whether the queue is empty. The servicing processor maydetermine that a queue is empty by checking the value of an empty queueflag or by checking the head pointer to see if it has a zero value. Ifthe queue is not empty, the servicing processor reads both the headpointer and the tail pointer to determine if the head pointer and thetail pointer both point to the same buffer, which indicates that thebuffer is the last buffer of the queue. The servicing processortransmits the data of the last buffer and sets both the head pointer andthe tail pointer to a null or invalid value. Setting the head and tailpointers to a null value frees the last buffer of the queue to be usedby other queues.

[0009] When the queuing processor is to add a buffer to the queue, thequeuing processor checks to see if both the head pointer and the tailpointer have a null value, which indicates that the queuing processor isadding a buffer to an empty queue. If the queuing processor is adding abuffer to an empty queue, the queuing processor sets both the head andtail pointers to indicate the buffer that has been added to the queue.Thus, the queuing processor must read both the head and tail pointers todetermine when it is adding a data element to an empty queue, and theservicing processor must read both the head and tail pointers todetermine when it is emptying the queue. The head and tail pointers aretherefore used to determine when a queue enters or leaves an emptystate.

[0010] Because both processors require access to the head and tailpointers, the head and tail pointers are stored in shared memory. Whenthe servicing processor determines that it is removing the last bufferof the queue, the servicing processor performs an atomic memory accessto set the head and tail pointers to a null value so that the queuingprocessor can determine when the queue is empty. An atomic memory accessby one processor entails a read-modify-write operation wherein the otherprocessor is not allowed to access shared memory until theread-modify-write operation has completed. Similarly, the queuingprocessor performs an atomic memory access to set the head and tailpointers of an empty queue to the value of the memory location of thebuffer being added to the empty queue.

[0011] An atomic memory access by either of the producer and servicingprocessors prevents the other processor from accessing the head and tailpointers. Therefore, when buffers are to be rapidly added to and removedfrom the queue, the use of shared memory to store the head and tailpointers is undesirable because a processor must be stalled to allow anatomic access of the shared memory to complete.

[0012] Although cache memories may be used to locally store data that isalso stored in shared memory, there would be problems with storing headand tail pointers in cache memories when both processors must read boththe head and tail pointers prior to manipulating the queue. This isbecause the queuing processor independently updates the tail pointer,and the servicing processor independently updates the head pointer. Forhigh-speed systems, the head and tail pointers are rapidly andindependently updated, which would result in frequent cache misses dueto stale data and excessive overhead to maintain cache coherency byflushing and refilling. If the cache coherence operations did not resultin a system failure, the use of caches to store head and tail pointerswould be inefficient compared to merely using shared memory.

SUMMARY AND OBJECTS OF THE INVENTION

[0013] It is therefore an object of the present invention to decouplethe head pointer from the tail pointer such that the queuing processoris only required to read the tail pointer and the servicing processor isonly required to read the head pointer.

[0014] It is a further object of the present invention to provide amethod for managing head and tail pointers wherein the head and tailpointers may be efficiently stored in cache memories or internalregisters.

[0015] These and other objects of the invention are provided by a methodfor managing a buffer queue that stores a data queue, wherein the dataqueue comprises a set of n data elements, n being at least zero. A headpointer is stored at a first location, which may be in a cachecontrolled by a first processor. The head pointer indicates a headbuffer of the buffer queue. The first processor reads the head pointerto determine the head buffer of the buffer queue when a data element isto be removed from the data queue. The first processor reads a nextpointer of the head buffer to determine whether the data queue is empty.The first processor determines that the data queue is empty when thenext pointer has a first value, which indicates that the head buffer isa dummy buffer.

[0016] Other objects, features, and advantages of the present inventionwill be apparent from the accompanying drawings and from the detaileddescription which follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

[0018]FIG. 1 shows a digital communications network.

[0019]FIG. 2 shows a service module of the digital communicationsnetwork.

[0020]FIG. 3 shows a buffer queue.

[0021]FIG. 4 shows an exemplary buffer format

[0022]FIG. 5 shows a buffer descriptor of an exemplary buffer.

[0023]FIG. 6 shows a general “recycle-then-read” buffer managementmethod.

[0024]FIG. 7 shows a general “read-then-recycle” buffer managementmethod.

[0025]FIG. 8 shows a buffer management method according to oneembodiment.

[0026]FIGS. 9A, 9B, 9C, 9D, 9E; 9F, and 9G illustrate the operation ofthe method shown in FIG. 8.

[0027]FIG. 10 shows a buffer management method according to oneembodiment.

[0028]FIGS. 11A, 11B, 11C, 11D, 11E, and 11F illustrate the operation ofthe method shown in FIG. 10.

DETAILED DESCRIPTION

[0029] A number of terms are used consistently herein. A “data queue” isa queue of data elements, such as the cells of a cell switching network,and “data queue length” refers to the length of a data queue. An “emptydata queue” is a data queue containing no data elements. A “bufferqueue” is a queue of buffers used to store a data queue. Typically, eachbuffer stores at least one data element, and a buffer that stores a dataelement is called a “data buffer.” A “dummy buffer” is a buffer thatstores invalid data and is provided such that a buffer queue that storesan empty data queue comprises at least one buffer. Thus, a buffer queuecannot be empty, and the head and tail pointers of a buffer queue aremade independent of one another. The prior method for queue managementdescribed above does not distinguish between data queues and bufferqueues because the number of buffers is always equal to the number dataelements, and an empty data queue results in an empty buffer queue,requiring the setting of the head and tail pointers to a null value.

[0030] One or more dummy buffers are provided for each buffer queue suchthat the buffer queue cannot become empty, even when the buffer queuecurrently stores no data elements. Because the head and tail pointersalways point to a buffer, there is no need to perform an atomic memoryaccess when a data queue becomes empty or when a data element is addedto a data queue. Therefore, neither processor is required to read boththe head and tail pointers, and the tail and head pointers thereforeneed not be stored in a shared memory location. Instead, the tailpointer may be stored in a first cache associated with and controlled bythe queuing processor, and the head pointer may be stored in a cacheassociated with and controlled by the servicing processor. Wherein theuse of a dummy buffer in a buffer queue effectively requires that atleast one buffer of the buffer pool is always in use, the ability tocache the head and tail pointers counterbalances the inability torecycle all buffers of the buffer pool and yields a substantialadvantage over prior methods.

[0031]FIG. 1 shows a digital communications network 10. Digitalcommunications network 10 includes a service module 15 that acts as abridge or gateway between customer premise equipment (CPE) 20 andbroadband network 25. CPE 20 may comprise any type of network andassociated network equipment For example, CPE 20 may be a frame relaysystem or an asynchronous transfer mode (“AIM”) network. CPE 20equipment may therefore be connected to service module 15 by one or moreT1 or E1 communication lines. Broadband network 25 is typically a largetelecommunications network that connects the CPE 20 to remote sites.Broadband network 25 may be any type of broadband network, such as anetwork using equipment sold by Stratacom®, Inc., of San Jose, Calif.

[0032] Service module 15 operates according to a servicing algorithm forregulating traffic between CPE 20 and broadband network 25. Typically,CPE 20 has a “service contract” that limits the amount of bandwidth ofbroadband network 25 that CPE 20 may use to send data to remote sites.Service module 15 therefore monitors the amount of “ingress” trafficdirected to broadband network 25 to better ensure that the limitsdefined by the service contract are not exceeded Service module 15 alsomonitors “egress” traffic directed from broadband network 25.

[0033] The methods described herein may find practical operation in anysetting wherein multiple processors manage a queue of buffers forstoring data elements; however, digital communications network 10 shownin FIG. 1 provides an excellent example for the application of thepresently described methods. As service module 15 is responsible forregulating traffic flow between CPE 20 and broadband network 25, servicemodule 15 is responsible for queuing the cells that are transmittedbetween CPE 20 and broadband network 25 to better ensure that cells arenot lost. The methods described herein may also be applied in systemswherein a single processor performs the functions of both the servicingprocessor and the queuing processor for the same queue of buffers;however, the methods provide greater advantages and are more efficientin multiprocessor systems.

[0034]FIG. 2 shows service module 15 in greater detail. As shown,service module 15 includes separate ingress buffer queues 30 and egressbuffer queues 35 Due to the nature of networks, there are typicallymultiple ingress buffer queues and multiple egress buffer queues, onefor each logical port or “virtual connection” of CPE 20 and broadbandnetwork 25 that routes its traffic through service module 15. Forexample, a single T1 trunk provides a maximum of twenty-four virtualconnections at a transfer rate of 64 kbps each.

[0035] Service module 15 is shown as including a processor 40 having acache 41 and a processor 45 having a cache 46. Processor 40 isresponsible for queuing ingress data. If CPE 20 comprises a network thatdoes not use cell switching, such as a frame relay network, processor 40may perform protocol translation and segmentation to reduce incomingframe relay packets to cells for transfer via broadband network 25.Alternatively, processor 40 may simply queue the incoming frames whereinprocessor 45 transmits the data of a queued frame on a cell-by-cellbasis. If CPE 20 comprises a cell-switching network such as an ATMnetwork, processor 40 need merely add the cells to the ingress bufferqueues. Processor 40 is also responsible for removing incoming cellsfrom the egress buffer queues. Thus, processor 40 acts as the queuingprocessor for ingress buffer queue 30 and the servicing processor foregress buffer queue 35.

[0036] Processor 45 is responsible for implementing the servicingalgorithm of service module 15, for removing outgoing cells from theingress buffer queues, and for queuing incoming cells in the egressbuffer queues. Processor 45 is therefore the servicing processor foringress buffer queue 30 and the queuing processor for egress bufferqueue 35.

[0037] Both processor 40 and processor 45 are shown as being coupled toingress buffer queue 30 and egress buffer queue 35, and the manner ofthe connection shown in FIG. 2 implies the roles of processor 40 andprocessor 45 in the queue management of the ingress and egress bufferqueues. For example, processor 40 maintains tail pointers for ingressbuffer queues 30 and head pointers for egress buffer queues 35, andprocessor 45 maintains head pointers for ingress buffer queues 30 andtail pointers for egress buffer queues 35. The tail pointers for ingressbuffer queues 30 and the head pointers for egress buffer queues 35 arestored in cache 41 of processor 40. Similarly, the head pointers ofingress buffer queues 30 and the tail pointers of egress buffer queues35 are stored in cache 46 of processor 45.

[0038] Wherein caches 41 and 46 are shown as being internal to therespective processors, caches 41 and 46 may be external to theprocessors. Furthermore, the head and tail pointers may alternatively bestored by internal registers of the queuing and servicing processors, orby external registers. Because the head and tail pointers areindependent from one another, many of the advantages of the presentlydescribed methods may be achieved by storing the head and tail pointersin non-shared memory locations such that atomic memory accesses are notrequired.

[0039]FIG. 3 shows an ingress buffer queue 30 in more detail. Ingressbuffer queue 30 is shown as being stored by a buffer pool 50. Bufferpool 50 comprises a plurality of memory locations or “buffers” of fixedsize, each for storing a data element such as a cell. Buffer pool 50 maybe implemented as one or more memory devices such as DRAMs.

[0040] No ordering is required or implied by the memory addresses of thebuffers. Instead, the buffers in a queue are linked to one another as alinked list using next pointers such as next pointers 62 and 67. For theexample shown in FIG. 3, a queue of three buffers is shown. Buffer 60 isindicated as the head buffer of the queue by the head pointer 48 storedin cache 46. Buffer 70 is shown as the tail buffer as indicated by thetail pointer 43 stored in cache 41.

[0041] The next pointer 62 of buffer 60 indicates that buffer 65 is thenext buffer in the queue, and next pointer 67 indicates that buffer 70is the next buffer after buffer 65. Wherein the next pointers are showngraphically as arrows linking one buffer to the next buffer, accordingto one embodiment, each next pointer comprises the address of the nextbuffer in the buffer queue. The information of the next pointers may bestored by the buffers or by a separate array of memory locations.According to the present embodiments, each next pointer is stored as apart of a buffer. FIG. 4 shows an exemplary buffer format. Buffer 60 isshown as storing a cell 90 and a buffer descriptor 95. FIG. 5 shows thatthe buffer descriptor includes the next pointer 62 that points to buffer65 and routing information 100.

[0042] Each of the ingress and egress buffer queues includes one or more“dummy” buffers such that each buffer queue always includes at least onebuffer, even when the data queue stored by the buffer queue is empty. Adummy buffer is an “empty” buffer that stores invalid data. A dummybuffer may be provided in one of at least two ways: 1) a buffer that hastransmitted its contents is not recycled and remains as the head buffer;and 2) a designated dummy buffer is provided wherein the dummy buffer isalways the last buffer of the buffer queue.

[0043]FIG. 6 is a flow chart of a general method for managing a bufferqueue when removing a data element from the stored data queue. Themethod of FIG. 6 is a “recycle-then-read” process that presumes that thehead buffer is “empty” (a dummy buffer) when the servicing processor isenabled to transmit a data element of the data queue. The process beginsat block 605 when the servicing processor is enabled to transmit thenext data element of the data queue. At process block 610, the currenthead buffer pointed to by the head pointer is recycled by setting thehead pointer to point to the buffer indicated by the next pointerassociated with the current head buffer. Thus, a new head buffer isindicated by the head pointer. At process block 615, the contents of thenew head buffer are read, and the process ends at process block 620. Thenew head buffer is “empty,” and the head pointer continues to point tothe new head buffer until the next data element is to be removed fromthe buffer queue. Therefore, the head pointer always points to a dummybuffer when the buffer read transaction is initiated, and a buffer queuethat is managed according to the method shown by FIG. 6 includes n+1buffers for storing data queue comprising a set of n data elements,wherein n is equal to zero or more.

[0044]FIG. 7 is a flow chart showing an alternative method for managinga buffer queue when removing a data element from the stored data queue.The difference between the methods shown in FIG. 6 and FIG. 7 is thestate of the buffer queue when a data element is to be removed from thedata queue. The method of FIG. 7 is a “read-then-recycle” processresults in the buffer queue storing a dummy buffer when the data queuebecomes empty. The process begins at process block 705 when theservicing processor is enabled to transmit a data element stored by abuffer of the buffer queue. At process block 705, the data elementstored by the current head buffer is read, and the current head bufferis recycled at process block 715. The process ends at process block 720.

[0045] According to the method shown in FIG. 7, the head pointer pointsto a dummy buffer when the data queue stored by the buffer queue isempty. The head pointer continues to point to a dummy buffer as dataelements are added to the data queue (and buffers are added to thebuffer queue) until the servicing processor is enabled to read dataelements from the stored data queue. Thus, a buffer queue that ismanaged according to the method of FIG. 7 may use either n buffers orn+1 buffers, depending on whether the buffer queue was recently emptiedof data elements.

[0046] One mechanism for detecting that the head buffer is a dummybuffer is to maintain a count of the number of data elements in the dataqueue such that the servicing processor is not allowed to read a dummybuffer queue. This helps to prevent the contents of the dummy bufferfrom being inadvertently transmitted as valid data by the servicingprocessor. For example, the servicing processor may maintain a valuerepresentative of the data queue length. If the data queue length iszero, the servicing processor will not allow the buffer queue thatstores the empty data queue to be read.

[0047] An alternative mechanism for detecting that the head buffer is adummy buffer requires that the servicing processor sets an empty flagupon detecting that the next pointer of the buffer to be recycled has aninvalid or null value, which indicates that the current head buffer isthe last buffer of the queue. While the empty flag is set, the headbuffer is a dummy buffer, and the servicing processor skips processblock 710 and immediately reads the next pointer of the dummy buffer atprocess block 715. When the queuing processor adds a data element to anempty data queue, the queuing processor writes the address of the newbuffer to the next pointer of the dummy buffer. If the servicingprocessor detects that the next pointer of the dummy buffer points toanother buffer, the servicing processor clears the empty flag, resetsthe head pointer to point to the new buffer, and performs the steps ofprocess blocks 710 and 715.

[0048] Thus far, the described mechanisms for detecting an empty dataqueue assume that dummy buffers are merely empty head buffers that havenot been recycled. Another alternative is to specify a buffer as a dummybuffer such that the servicing processor may detect that the head bufferis the dummy buffer by merely comparing the value of the head pointer tothe addresses of known dummy buffers. Upon determining that the headbuffer is a dummy buffer, the servicing processor monitors the nextpointer of the dummy buffer as described above. Thus, the head pointeritself acts as a form of empty flag.

[0049]FIG. 8 is a flow chart showing a more detailed “recycle-then-read”queue management process such as that described with respect to FIG. 6.The process begins at process block 805 when the servicing processor isenabled to remove a data element from the data queue. At process block810, the servicing processor reads the head pointer, which may be storedin a cache associated with the servicing processor. At process block815, the servicing processor reads the next pointer of the head bufferindicated by the head pointer. At process block 820, it is determinedwhether the value of the next pointer is invalid or null, indicatingthat no data elements remain in the data queue and that the head bufferis a dummy buffer. If the next pointer has a null value, the processends at process block 825 because the data queue is empty. The queuingprocessor updates the next pointer of the dummy buffer to point to thebuffer that stores the new data element because the dummy buffer is thetail buffer of the buffer queue. Thus, the servicing processor detectsthat a previously empty data queue is no longer empty when the nextpointer of the dummy buffer points to another buffer, and the dummybuffer can be recycled. Process blocks 820 and 825 may be omitted if aseparate mechanism is provided that prevents the enabling of theservicing processor when the data queue is empty. For example, theservice module may maintain a value indicative of the data queue length.If the value of the data queue length is zero, the data queue is empty,and the queue will not be serviced.

[0050] If the next pointer of the head buffer points to another buffer,the servicing processor sets the head pointer to point to that buffer atprocess block 830. Thus, there is a new head buffer. The “old” headbuffer is recycled, and the servicing processor reads the data elementcontained in the new head buffer at process block 835. The process endsat process block 840. The steps of process blocks 805-840 are repeatedfor each data element to be removed from the data queue.

[0051] FIGS. 9A-9G illustrate the process shown in FIG. 8. FIG. 9A showsan empty data queue wherein both the head pointer and the tail pointerpoint to a dummy buffer, which is shown as being buffer 60. FIG. 9Bshows a first buffer being added to the buffer queue, indicating thatthe data queue now contains one data element. As shown, the queuingprocessor updates the next pointer 62 of dummy buffer 60 to point tobuffer 65. The queuing processor a updates the tail pointer to indicatebuffer 65 as the tail buffer. The tail pointer may be stored in a cacheassociated with the queuing processor. The next pointer of the tailbuffer by default contains a null or invalid value that indicates thatno further buffers remain in the buffer queue. The head pointercontinues to point to the head buffer, indicating that the servicingprocessor has not yet been enabled to remove a data element from thedata queue. FIG. 9C shows buffer 70 as being added to the buffer queue.The next pointer 67 of buffer 65 is updated to indicate buffer 70 as thenext buffer in the buffer queue, and the tail pointer indicates buffer70 as the tail buffer.

[0052]FIG. 9D shows the head pointer as pointing to buffer 65,indicating that the servicing processor was enabled to remove a dataelement from the data queue, determined that the next pointer 62 pointedto a buffer, and reset the head pointer to indicate buffer 65 and torecycle buffer 60. The servicing processor reads the data element storedby buffer 65 and maintains the head pointer as pointing at buffer 65such that buffer 65 becomes a dummy buffer as shown in FIG. 9E. In FIG.9F, buffer 65 is recycled, and the head and tail pointers both indicatebuffer 70. After the data element is read from buffer 70, buffer 70becomes a dummy buffer as shown in FIG. 9G. Thus, the data queue isempty. Should the servicing processor be enabled to remove another dataelement from the data queue, the servicing processor detects an emptyqueue by reading the next pointer of dummy buffer 70.

[0053]FIG. 10 shows a more detailed “read-then-recycle” queue managementmethod such as that shown in FIG. 7. The process begins at process block1005 when the servicing processor is enabled to remove a data elementfrom the data queue stored by the buffer queue. At process block 1010,the servicing processor checks an empty flag to determine if the storeddata queue is empty. If the servicing processor determines at processblock 1015 that the data queue is empty, servicing processor performsthe steps shown in process blocks 1050-1075, as described below.

[0054] Assuming that the data queue is not empty, the servicingprocessor reads the head pointer at process block 1020. At process block1025, the servicing processor transmits the data element stored by thehead buffer. At process block 1030, the servicing processor reads thenext pointer of the head buffer. If the servicing processor determinesat process block 1035 that the next pointer does not point to anotherbuffer, the data queue is empty, and the servicing processor sets theempty flag at process block 1080, and the process ends at process block1085. At process block 1040, if the data queue is not empty, theservicing processor sets the head pointer to point to the bufferindicated by the next pointer of the head buffer. There is therefore anew head buffer, and the old head buffer is recycled. The process endsat process block 1045.

[0055] If the empty flag was set at process block 1015, the servicingprocessor reads the head pointer at process block 1050 and the nextpointer of the head buffer (which is a dummy buffer) indicated by thehead pointer at process block 1055. If the servicing processordetermines at process block 1060 that the next pointer of the dummybuffer is null, the data queue is empty, and the process ends at processblock 1070. The next pointer of the dummy buffer is updated by thequeuing processor when a data element is added to an empty data queuebecause the dummy buffer is also the tail buffer of the buffer queue. Atprocess block 1075, if the queuing processor has added a data element tothe previously empty data queue, the servicing processor sets the headpointer to point to the buffer indicated by the next pointer of thedummy buffer, and the dummy buffer is recycled. The process continues atprocess block 1020. The process steps shown by process blocks 1005-1010and 1050-1075 are not required if a separate mechanism is provided toensure that the servicing processor is not allowed to read from an emptydata queue. For example, the service module may maintain a valueindicative of the data queue length that is checked to detect an emptydata queue, wherein servicing of the data queue is prevented if the dataqueue is empty.

[0056] FIGS. 11A-11F illustrate the method described with respect toFIG. 10, FIG. 11A shows an empty data queue such as that shown in FIG.9A wherein an empty flag 80 is set. As shown in FIG. 11B, the queuingprocessor has added three data elements to the data queue. Next pointer62 of dummy buffer 60 points to buffer 65; next pointer 67 of buffer 65points to buffer 70; and next pointer 72 of buffer 70 points to buffer75, which is the last buffer of the buffer queue. The head pointercurrently points to dummy buffer 60, and the tail pointer points tobuffer 75.

[0057] As shown in FIG. 11C, the servicing processor has been enabled toremoved data elements from the data queue. Buffer 60 has been recycled,and the head pointer points to buffer 65. The empty flag has been reset.The servicing processor reads the data element of buffer 65 and thenreads the next pointer of buffer 65, allowing buffer 65 to be recycled.Thus, FIG. 11D shows the head pointer as pointing to buffer 70. Theservicing processor reads the data element of buffer 70 and then readsthe next pointer of buffer 70, allowing buffer 70 to be recycled.

[0058]FIG. 11E shows the head pointer as pointing to buffer 75. The tailpointer also points to buffer 75, which still stores a valid dataelement such that the data queue is not empty. The servicing processorreads the data element of buffer 75 and then reads the next pointer ofbuffer 75. Upon determining that buffer 75 is the last buffer in thebuffer queue, the servicing processor sets the empty flag 80 to indicatean empty data queue, as shown in FIG. 11F.

[0059] In the foregoing specification the invention has been describedwith reference to specific exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of theinvention. The specification and drawings are, accordingly, to beregarded in an illustrative rather than restrictive sense.

What is claimed is:
 1. A circuit comprising a buffer queue that stores adata queue, a first processor including a first cache coupled to thebuffer queue, and a second processor including a second cache coupled tothe buffer queue, the first processor storing a head pointer of thebuffer queue in the first cache and the second processor storing a tailpointer of the buffer queue in the second cache.
 2. The circuit of claim1, wherein the head pointer and the tail pointer point to a dummy bufferwhen the data queue is empty.
 3. A circuit comprising a buffer queuethat stores a data queue, a first processor coupled to the buffer pool,and a second processor coupled to the buffer pool, the first processorincluding a first memory location that stores a head pointer of thebuffer queue and the second processor includes a second memory locationthat stores a tail pointer of the buffer queue, the head pointer and thetail pointer always pointing to a buffer.
 4. The circuit of claim 3,wherein the first memory location is a first cache controlled by thefirst processor, and the second memory location is a second cachecontrolled by the second processor.
 5. The circuit of claim 3, whereinthe first memory location is a first internal register controlled by thefirst processor, and the second memory location is a second internalregister controlled by the second processor.
 6. A method for managing abuffer queue that stores a data queue, wherein the data queue comprisesa set of n data elements, n being at least zero, the method comprisingthe steps of: storing a head pointer at a first location, the headpointer indicating a head buffer of the buffer queue; a first processorreading the head pointer to determine the head buffer of the bufferqueue when a data element is to be removed from the data queue; thefirst processor reading a next pointer of the head buffer; and the firstprocessor determining that the data queue is empty when the next pointerhas a first value, which indicates that the head buffer is a dummybuffer.
 7. The method of claim 6, further comprising the steps of: thefirst processor setting the head pointer to point to a new head bufferwhen the next pointer has a second value indicative of the new headbuffer; the first processor reading a first data element of the dataqueue stored by the new head buffer; and the first processor maintainingthe head pointer to indicate the new head buffer.
 8. The method of claim6, further comprising the steps of. storing a tail pointer in a secondlocation, the tail pointer indicating the head buffer as being a tailbuffer of the buffer queue; a second processor adding a new data elementto the data queue wherein the second processor adds a new tail buffer tothe buffer queue, the new tail buffer storing the new data element; thesecond processor updating the tail pointer to indicate the new tailbuffer as being the tail buffer; and the second processor updating thenext pointer of the head buffer to have a second value indicating thenew tail buffer.
 9. The method of claim 6, further comprising the stepsof: initially determining whether the data queue is empty; and the firstprocessor reading a first data element stored by the head buffer priorto the step of the first processor reading the next pointer of the headbuffer.
 10. The method of claim 6, wherein the next pointer is stored aspart of the head buffer, the step of reading the next pointer comprisingthe step of reading the head buffer.
 11. The method of claim 6, whereinthe step of storing the head pointer in a first location comprises thestep of the first processor storing the head pointer in a first cachememory controlled by the first processor.
 12. The method of claim 6,wherein the first processor sets an empty flag to indicate that the dataqueue is empty upon determining that no buffers other than the headbuffer remain in the buffer queue.
 13. The method of claim 8, whereinthe step of storing the tail pointer in a second location comprises thestep of the second processor storing the tail pointer in a second cachememory controlled by the second processor.
 14. A circuit for managing abuffer queue that stores a data queue comprising a set of n dataelements, the circuit comprising. a first memory storing a head pointerindicating a head data element of the queue; a first processor coupledto the first memory for removing data elements from the data queue, forreading the head pointer to determine a head buffer of the buffer queuewhen a data element is to be removed from the data queue, for reading anext pointer of the head buffer, and for determining that the data queueis empty when the next pointer has a first value, which indicates thatthe head buffer is a dummy buffer.
 15. The circuit of claim 14, thefirst processor for setting the head pointer to point to a new headbuffer when the next pointer has a second value indicative of the newhead buffer, for reading a first data element of the data queue storedby the new head buffer, and for maintaining the head pointer to indicatethe new head buffer.
 16. The circuit of claim 14 further comprising: asecond memory for storing a tail pointer, the tail pointer indicatingthe head data element as being a tail data element of the queue; asecond processor for adding a new data element to the queue, forupdating the tail pointer to indicate a new tail buffer that stores thenew data element as being the tail buffer, and for updating the nextpointer of the head buffer to have a second value indicating the newtail buffer, wherein the first processor updates the head pointer toindicate the new data element as being the head data element in responseto detecting that the next pointer has the second value.
 17. The circuitof claim 14, wherein the first memory is a first cache controlled by thefirst processor.
 18. The circuit of claim 16, wherein the second memoryis a second cache controlled by the second processor.
 19. A circuit formanaging a buffer queue for storing a data queue comprising a set of ndata elements, wherein n is at least zero, the circuit comprising: abuffer pool including a plurality of buffers; a first processor coupledto the buffer pool; a first memory location coupled to and accessed bythe first processor, the first memory location storing a head pointerindicative of a head buffer of the buffer queue, wherein the headpointer always points to a buffer; a second processor coupled to thebuffer pool; a second memory location coupled to and accessed by thesecond processor, the second memory location storing a tail pointerindicative of a tail buffer of the buffer queue, wherein the secondprocessor adds buffers of the buffer pool to the buffer queue and thefirst processor removes buffers from the buffer queue and returns themto the buffer pool.
 20. The circuit of claim 19 wherein the tail pointeralways points to a buffer.
 21. The circuit of claim 19, wherein thefirst memory location is a first cache memory internal to the firstprocessor and the second memory location is a second cache memoryinternal to the second processor.
 22. The circuit of claim 19, whereinthe first memory location is a first rester internal to the firstprocessor and the second memory location is a second register internalto the second processor.